The present invention relates generally to the field of integrate circuit manufacturing and more particularly to testing an integrated circuit using dedicated function pins in a non-dedicated function test mode.
A distributed memory refers to a multiprocessor computer system in which each processor has its own private memory. Computational tasks can only operate on local data, and if remote data is required, the computational task must communicate with one or more remote processors. Memory devices (e.g., NVRAM, DRAM, etc.) are a type of integrated circuit (IC) that can be used to store data.
Traditionally, IC devices have been tested using automated test equipment (ATE) where the IC pins being used exclusively for dedicated function testing. Joint Test Action Group (JTAG) protocol and JTAG Testing Access Port (TAP) is used for testing of IC chips after manufacturing. Therefore, most IC chips have JTAG TAP support.
In a distributed memory buffer system consisting of an address and command chip and multiple data chips, all chips must have some method of testing to ensure proper functionality. However, it can be difficult when there is not enough space for a JTAG TAP on each chip. When the chips are pin constrained, it becomes a more difficult task.
Hence, there exists a need to improve circuit testing in a distributed memory buffer system using JTAG methods and equipment.